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| Agilent HCPL-8100/0810 High Current Line Driver Data Sheet Features * 1 APP driving current * * * 3.5 MHz gain bandwidth product - 60 dB maximum harmonic distortion Load detection function Under-voltage detection Over-temperature shutdown 5 V single supply Temperature range: -40C to +85C Suitable for FCC Part 15 and EN50065-1 compliant design Description The HCPL-8100 and HCPL0810 are low-cost high current line drivers. With a 5 V single supply, they deliver up to 1 APP current. This is ideal for high current applications such as a Powerline modem. The HCPL-8100 and HCPL0810 are internally protected against over-temperature conditions through thermal shutdown. Under-voltage or over-load condition is sensed by internal detection circuit and indicated by Status pin output. In addition, with the transmit enable (Tx-en) input, the line driver output stage can be disabled to reduce power dissipation when not operating. The HCPL-8100 and HCPL0810 are specified for operation over extended temperature range from -40C to +85C. The HCPL8100 is available in DIP-8 package, and the HCPL-0810 is available in SO-8 package. * * * * * Applications * Automatic meter reading (AMR) * * * * Powerline modem General purpose line driver Signal conditioning Digital-to-analog converter buffers Connection Diagram STATUS TX -EN TX PLM Transceiver Filter 1 2 3 4 Status Tx -en Tx -in R ref Tx -out V CC GND GND 8 7 6 5 5V L N HCPL-8100/0810 CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and /or degradation which may be induced by ESD. Package Pin Out Pin Descriptions 1 2 3 4 Status Tx-en Tx-in R ref Tx-out VCC GND GND 8 7 6 5 Pin No. Symbol Function 1 Status Line condition detection 2 Tx-en 3 4 5, 6 7 8 Tx-in Rref GND VCC Tx-out Description A logic high indicates line conditions such as - under-voltage when VCC < 4 V - load detection when ITx-out < -0.25 A - over-temperature (thermal shutdown) Transmit enable A logic high enables the Tx-out; A logic low disables the Tx-out and changes it to high impedance state Transmit input Transmit signal input Resistor reference Sets line driver biasing current, typically 24 k Power supply ground Power supply and signal ground 5 V power supply 5 V power supply Transmit output Transmit signal output, to be enabled by Tx-en Block Diagram Under-Volt Detection Status 1 Status Output Load Detection Over-Temp Detection 7 VCC 6 GND Tx-en 2 5 GND Tx-in 3 Amp 8 Tx-out Rref 4 Ordering Information Specify part number followed by option number (if desired). Example: HCPL-8100 HCPL-0810-XXX No option = SO-8 package, 100 units per tube. 500 = Tape and Reel Packaging Option, 1500 units per reel. Standard 8-pin DIP package, 50 units per tube. 2 Package Outline Drawings HCPL-8100 Standard 8-pin DIP package 9.50 0.05 (0.374 0.002) 8 7 6 A 8100 YYWW 1 1.19 (0.047) MAX. 2 3 4 1.524 (0.060) MAX. 6.62 0.05 (0.260 0.002) 7.87 0.25 (0.310 0.010) 5 DATE CODE 3.92 (0.155) MAX. 0.381 (0.015) MIN. 3.05 (0.120) MIN. 0.20 (0.008) 0.35 (0.014) 1.094 0.320 (0.037 0.013) 0.555 (0.022) MAX. 2.54 0.25 (0.100 0.010) 5 TYP. DIMENSIONS IN MILLIMETERS AND (INCHES) HCPL-0810 Small Outline SO-8 Package DIMENSIONS IN MILLIMETERS AND (INCHES) 3 Solder Reflow Temperature Profile 300 PREHEATING RATE 3C + 1C/- 0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C PEAK TEMP. 230C 2.5C 0.5C/SEC. 160C 150C 140C 3C + 1C/- 0.5C 30 SEC. 30 SEC. SOLDERING TIME 200C TEMPERATURE (C) 200 100 PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 TIME (SECONDS) 150 200 250 Absolute Maximum Ratings Parameter Storage Temperature Ambient Operating Temperature Junction Temperature Supply Voltage Output Voltage Tx-in Voltage Tx-en Voltage Solder Reflow Temperature Profile Symbol TS TA TJ V CC VO V Tx-in V Tx-en Min. -55 -40 -0.5 -0.5 -0.5 -0.5 Max. 125 85 150 5.5 V CC V CC V CC Unit C C C Volts Volts Volts Volts (See Solder Reflow Temperature Profile Section) Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltage Symbol TA VCC Min. -40 4.75 Typ. 25 5 Max. 85 5.25 Unit C V 4 Electrical Specifications Unless otherwise noted, for sinusoidal waveform input and reference resistor Rref = 24 k, all typical values are at TA = 25C and VCC = 5 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter VCC Supply Current Symbol Min. ICC Typ. 1.2 20 Max. 2 45 4.3 Unit mA mA V C APP Test Condition VTx-en = 0 V, VTx-in = 0 VPP, Tx-out no load VTx-en = 5 V, VTx-in = 0 VPP, Tx-out no load Fig. 1 2, 3 Note VCC Under Voltage Detection Junction OverTemperature Threshold Load Detection Threshold Status Logic High Output Status Logic Low Output Power Supply Rejection Ratio DC Bias Voltage Output Impedance VUVD 3.8 4.0 150 0.5 1 2 VTx-en = 5 V, VTx-in = 1.25 VPP, f = 132 kHz, Gain = - 2, RL = 2.5 VCC = 3.5 V, IOH = - 4 mA VCC = 5 V, IOL = 4 mA 50 Hz ripple, Vripple = 200 mVPP, VTx-en = 5 V, VTx-in = 0 VPP, Tx-out no load VTx-en = 5 V, Tx-out no load VTx-en = 0 V, VTx-in = 0 VPP, open loop, f = 132 kHz VTx-en = 5 V, VTx-in = 0 VPP, f = 132 kHz VTx-en = 5 V, VTx-in = 1 VPP, RL = 50 VTx-in = 1 VPP, f = 132 kHz, Tx-out no load VTx-en = 5 V, VTx-in = 1.75 VPP, f = 132 kHz, Tx-out no load VTx-en = 0 V, VTx-in = 1.75 VPP, f = 132 kHz, Tx-out no load VTx-en = 5 V, VTx-out = 3.5 VPP, f = 132 kHz, Gain = -2, Rref = 24 k , RL= 50 4, 14 12, 13 3 VOH VOL PSRR VBias ZO VCC-1 0 72 2.27 12 0.5 VCC 0.8 V V dB V k MHz Gain Bandwidth Product Transmit Enable Threshold Voltage Tx Enable Time Tx Disable Time 2nd Harmonic Distortion 3rd Harmonic Distortion Output Current Thermal Resistance (HCPL-8100) Thermal Resistance (HCPL-0810) GBW Vth, Tx tTx-en 0.8 3.5 2.4 0.9 0.2 V s s 11, 15 15 5-10, 16 HD2 HD3 IO JA JA -65 -75 1 100 60 138 70 -60 -65 dB dB APP VTx-en = 5 V, f=132 kHz 4 C/W 1 oz. trace, 2-layer PCB, still air, TA = 25C C/W 1 oz. trace, 4-layer PCB, still air, TA = 25C C/W 1 oz. trace, 2-layer PCB, still air, TA = 25C C/W 1 oz. trace, 4-layer PCB, still air, TA = 25C Notes: 1. Threshold of falling VCC with hysteresis of 0.2 V (typ.). 2. Threshold of rising junction temperature with hysteresis of 20C (typ.). 3. See Application Information section for more information on the load detection feature. 4. See Figure 3 for the plot of supply current versus Tx output current. 5 Performance Plots Unless otherwise noted, all typical plots are at TA = 25C, VCC = 5 V, sinusoidal waveform input and Rref = 24 k. 3 VTx-en = 0 V 2.5 70 VTx-en = 55VV Tx-en = 60 ICC - SUPPLY CURRENT - mA 200 f = 132 kHz 180 ICC - SUPPLY CURRENT - mA ICC - SUPPLY CURRENT - mA 2 50 40 30 20 10 0 -50 R ref= 8 k(c) k ref R ref= 12 k(c) k ref R ref= 24 k(c) k ref -25 0 25 50 75 TA - AMBIENT TEMPERATURE - C 100 160 140 120 100 80 60 40 R ref = 8 k k(c) ref R ref = 12 k k(c) ref R ref = 24 k k(c) ref 0 0.2 0.4 0.6 0.8 1 1.2 1.5 1 R ref = 8 k k(c) ref R ref = 12 k k(c) ref k(c) R ref = 24 k ref -50 -25 0 25 50 75 100 0.5 0 TA - AMBIENT TEMPERATURE - C ITx-out - Tx OUTPUT CURRENT - APP Figure 1. Supply current vs. temperature for Tx disabled. 140 120 AOL - VOLTAGE GAIN - dB Figure 2. Supply current vs. temperature for Tx enabled. -60 HD - HARMONIC DISTORTION - dBc Figure 3. Supply current vs. Tx output current. 240 GAIN PHASE 210 180 150 120 90 60 R L = 50 (c) L 1 10 100 30 0 1 k 10 k 100 k 1 M 10 M PHASE - DEGREES -60 -64 -66 -68 -70 -72 -74 -76 -78 -80 -50 f = 50 kHz, Gain = -2, VTx-out = 3.5 VPP, RL = 50 -25 0 25 50 75 TA - AMBIENT TEMPERATURE - C 100 HD - HARMONIC DISTORTION - dBc -62 HD2 HD3 -62 -64 -66 -68 -70 -72 -74 -76 -78 -80 -50 f = 132 kHz, Gain = -2, VTx-out = 3.5 VPP, RL = 50 -25 HD2 HD3 100 80 60 40 20 0 -20 0.1 f - FREQUENCY - Hz 0 25 50 75 TA - AMBIENT TEMPERATURE - C 100 Figure 4. Gain and phase vs. frequency. Figure 5. Tx-out harmonic distortion vs. temperature for f = 50 kHz. Figure 6. Tx-out harmonic distortion vs. temperature for f = 132 kHz. -40 - 40 -40 HD - HARMONIC DISTORTION - dBc HD2 HD3 R ref = 24 k(c) k ref HD - HARMONIC DISTORTION - dBc -42 HD - HARMONIC DISTORTION - dBc -44 -46 -48 -50 -52 -54 -56 -58 -60 -50 f = 450 kHz, Gain = -2, -2, VTx-out = 3.5 VV PP LR= 50 (c) , Tx-out= 3.5 PP, R L = 50 -25 0 25 50 75 100 HD2 HD3 - 45 - 50 - 55 - 60 - 65 - 70 - 75 - 80 - 85 - 90 0 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0 HD2 HD3 R ref = 24 k(c) k ref R ref = 12 k(c) k ref R ref = 12 k(c) k ref R ref = 8 k(c) k ref Gain = -2, VTx-out = 3.5 VPP, RL = 50 50 100 150 200 250 300 350 400 450 500 f - FREQUENCY - kHz R ref = 8 k(c) k ref Gain = -4, VTx-out == 3.5 PP,PPL R L50 (c) -4, V Tx-out 3.5 V V R, = = 50 50 100 150 200 250 300 350 400 450 500 f - FREQUENCY - kHz TA - AMBIENT TEMPERATURE - C Figure 7. Tx-out harmonic distortion vs. temperature for f = 450 kHz. Figure 8. Tx-out harmonic distortion vs. frequency for different values of Rref at Gain = -2. Figure 9. Tx-out harmonic distortion vs. frequency for different values of Rref at Gain = -4. 6 -60 HD2 -62 HD3 -64 -66 -68 -70 -72 -74 R ref = 8 k(c) k ref R ref= 12 k(c) k -76 ref R ref = 24 k(c) k ref -78 -80 -82 -84 -86 f = 132 kHz, Gain = -2 Gain = -2, V Tx-out=3.5 VPP , ,RR == 50 (c) VTx-out = 3.5 V PP L L 50 -88 -90 -50 -25 0 25 50 75 100 TA - AMBIENT TEMPERATURE - C Tx-out (PIN 8) 0.5 A/DIV Tx-en (PIN 2) 2 V/DIV 2s/DIV HD - HARMONIC DISTORTION - dBc tth 2s/DIV Tx-out (PIN 8) 1 V/DIV tTx-en STATUS (PIN 1) 2 V/DIV tth Figure 10. Tx-out harmonic distortion vs. temperature for different values of Rref. Figure 11. Tx enable time. Figure 12. Tx-out load detection. 7 Test Circuit Diagrams Unless otherwise noted, all test circuits are at TA = 25C, VCC = 5 V, sinusoidal waveform input, and signal frequency f = 132 kHz. 20 k 1 F SCOPE 5V V IN = 1.25 VPP 100 nF 10 k R ref 1 2 3 4 Status Tx -en Tx -in R ref Tx -out V CC GND GND 8 7 6 5 100 F 100 nF 5V RL 2.5 HCPL-8100/0810 Figure 13. Load detection test circuit. 20 k 1 F 1 5V 100 nF 10 k V IN = 1 VPP f = 10 k ~ 10 MHz R ref 24 k 2 3 4 Status Tx -en Tx -in R ref Tx -out V CC GND GND 8 7 6 5 100 F 100 nF 5V V OUT RL 50 HCPL-8100/0810 Figure 14. Gain bandwidth product test circuit. 20 k 1 2 V IN = 1.75 VPP 100 nF PULSE GEN. V PULSE = 5 V, fPULSE 1 kHz St atus Tx -en Tx -in R ref Tx -out V CC GND GND 8 7 6 5 V OUT 5V 3 10 k R ref 24 k 4 100 F 100 nF HCPL-8100/0810 Figure 15. Tx enable/disable time test circuit. 20 k 1 F 1 5V V IN = 1.75 VPP 100 nF 10 k R ref 24 k 2 3 4 Status T x-en Tx -in R ref Tx -out V CC GND GND 8 7 6 5 100 F 100 nF 5V 50 SPECTRUM ANALYZER HCPL - 8100/0810 Figure 16. Tx-out harmonic distortion test circuit. 8 Application Information The HCPL-8100 and HCPL0810 are designed to work with various transceivers and can be used with a variety of modulation methods including Gain = - R2 / R1 STATUS TX-EN TX PLM Transceiver F ilter 100 nF Rref 24 k C1 R1 ASK, FSK and BPSK. Figure 17 shows a typical application in a powerline modem using Frequency Shift Keying (FSK) modulation scheme. R2 R3 2 C3 1 F L2 5V C5 100 F D1 C2 L X2 L1 330 H N 1 2 3 4 Status Tx-en Tx-in R ref Tx -out VCC GND GND 8 7 6 5 C4 100 nF HCPL - 8100/0810 Figure 17. Schematic of HCPL-8100 or HCPL-0810 application for FSK modulation scheme. Line Driver The line driver is capable of driving powerline load impedances with output signals up to 4 VPP. The internal biasing of the line driver is controlled externally via a resistor Rref connected from pin 4 to ground. The optimum biasing point value for modulation frequencies up to 150 kHz is 24 k. For higher frequency operation with certain modulation schemes, it may be necessary to reduce the resistor value to enable compliance with international regulations. The output of the line driver is coupled onto the powerline using a simple LC coupling circuit as shown in Figure 18. Refer to Table 1 for some typical component values. Capacitor C2 and inductor L1 attenuate the 50/60 Hz powerline transmission frequency. A suitable value for L1 can range in value from 200 H to 1 mH. To reduce the series coupling impedance at the modulation frequency, L2 is included to compensate the reactive impedance of C2. This inductor should be a low resistive type capable of meeting the peak current requirements. To meet many regulatory requirements, capacitor C2 needs to be an X2 type. Since these types of capacitors typically have a very wide tolerance range of 20%, it is recommended to use as low Q factor as possible for the L2/C2 combination. Using a high Q coupling circuit will result in a wide tolerance on the overall coupling impedance, causing potential communication difficulties with low powerline impedances. Occasionally with other circuit configurations, a high Q coupling arrangement is recommended, e.g., C2 less than 100 nF. In this case it is normally used as a compromise to filter out of band harmonics originating from the line driver. This is not required with the HCPL8100 or HCPL-0810. C3 Tx 1 F L1 N GND X2 L2 C2 L Figure 18. LC coupling network. Table 1. Typical component values for LC coupling network. Carrier LC Coupling Frequency (kHz) L2 (H) C2 (nF) 110 15 150 120 10 220 132 6.8 220 150 6.8 220 9 Although the series coupling impedance is minimized to reduce insertion loss, it has to be sufficiently large to limit the peak current to the desired level in the worst expected powerline load condition. The peak output current is effectively limited by the total series coupling resistance, which is made up of the series resistance of L2, the series resistance of the fuse and any other resistive element connected in the coupling network. To reduce power dissipation when not operating in transmit mode the line driver stage is shut down to a low power high impedance state by pulling the Tx-en input (pin 2) to logic low state. External Transient Voltage Protection To protect the HCPL-8100 and HCPL-0810 from high voltage transients caused by power surges and disconnecting/ connecting the modem, it is Table 2. Status pin logic necessary to add an external 6.8 V bi-directional transient voltage protector (as component D1 shown in Figure 17). Additional protection from powerline voltage surges can be achieved by adding an appropriate Metal Oxide Varistor (MOV) across the powerline terminals after the fuse. Internal Protection and Sensing The HCPL-8100 and HCPL0810 include several sensing and protection functions to ensure robust operation under wide ranging environmental conditions. The first feature is the VCC Under Voltage Detection (UVD). In the event of VCC dropping to a voltage less than 4 V, the output status pin is switched to a logic high state. The next feature is the overtemperature shutdown. This particular feature protects the line driver stage from over- temperature stress. Should the IC junction temperature reach a level above 150C, the line driver circuit will be shut down and the output of Status (pin 1) is pulled to the logic high state simultaneously. The final feature is load detection function. The powerline impedance is quite unpredictable and varies not just at different connection points but is also time variant. The HCPL-8100 and HCPL0810 include a current sense feature, which may be utilized to feedback information on the instantaneous powerline load condition. Should the peak current reach a level greater than 0.5 APP, the output of status pin is pulled to a logic high state for the entire period the peak current exceeds -0.25 A as shown in Figure 12. Using the period of the pulse together with the known coupling impedance, the actual powerline load can be calculated. Table 2 shows the logic output of the Status pin. Status output Normal Low VCC < 4 V High Over-Temperature High ITx-out < - 0.25 A High (pulsed) www.agilent.com/ semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright (c) 2004 Agilent Technologies, Inc. Replaces 5989-0573EN June 11, 2004 5989-1316EN |
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